With the increase of integration density of a semiconductor device, a geometric dimension of the semiconductor device or an internal wiring thereof is getting more miniaturized. Resistance of the internal wiring such as copper (Cu) wiring increases as the geometrical dimension of the Cu wiring decreases. In order to reduce such an increase of resistance, combined resistance of the barrier layer and the Cu wiring needs to be reduced by decreasing a thickness of a diffusion barrier film (hereinafter, simply referred to as a “barrier layer”) for preventing a diffusion of Cu.
The barrier layer is formed by using a PVD method (sputtering method), as described in Japanese Patent Laid-open Publication No. 2008-028046, for example.